Shared bit line smt mram array with shunting transistors between bit lines

ABSTRACT

An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

The present disclosure is a divisional application that claims priorityunder 35 U.S.C. §120 from U.S. patent application Ser. No. 12/803,523,filing date Jun. 29, 2010, now U.S. Pat. No. ______, issued ______,assigned to a common assignee and herein incorporated by reference inits entirety.

BACKGROUND

This disclosure relates generally to memory cells and array structuresfor memory cells. More particularly, this disclosure relates to magneticrandom access memory (MRAM) cells and array structures for spin momenttransfer (SMT) MRAM cells.

SUMMARY

The term spin moment transfer MRAM refers to a magnetic tunnel junction(MTJ) random access memory (RAM). In this context, the term “spin”refers to the angular momentum of electrons passing through an MTJ thatwill alter the magnetic moment of a free layer of an MTJ device.Electrons possess both electric charge and angular momentum (or spin).It is known in the art that a current of spin-polarized electrons canchange the magnetic orientation of a free ferromagnetic layer of an MTJvia an exchange of spin angular momentum.

“A Novel Nonvolatile Memory with Spin-torque Transfer MagnetizationSwitching: Spin-Ram”, Hosomi, et al., IEEE International ElectronDevices Meeting, 2005. IEDM Technical Digest. December 2005, pp.:459-462, provides a nonvolatile memory utilizing spin-torque transfermagnetization switching (STS), abbreviated Spin-RAM. The Spin-RAM isprogrammed by magnetization reversal through an interaction of a spinmomentum-torque-transferred current and a magnetic moment of memorylayers in magnetic tunnel junctions (MTJs), and therefore an externalmagnetic field is unnecessary as that for a conventional MRAM.

A spin-torque MTJ element has two ferromagnetic layers and a spacerlayer between the ferromagnetic layers. One ferromagnetic layer is apinned magnetic layer and the other ferromagnetic layer is a freemagnetic layer. The spacer layer is a tunnel barrier layer. When a spinpolarized electron flows through the ferromagnetic layers, the spindirection rotates according to the directions of magnetic moment. Therotation of spin direction of the electrons in the ferromagnetic layersis the origin of a spin-torque to the magnetic moment. If the giventorque is large enough, magnetization of ferromagnetic layer and thusthe magnetic moment is reversed. The magnetization of the ferromagneticlayers transforms from parallel to anti-parallel alignment. This changesthe MTJ element from a low resistance state to a high resistance statethus changing the logic state of the MTJ element from a first logicstate (0) to a second logic state (1). A voltage source provides theprogramming voltage that generates the programming current that isreversed appropriately change the programming state of the MTJ element.Reading an SMT MRAM cell involves applying a voltage across the SMT MRAMcell and detecting the resistance (or current) difference.

As illustrated in FIG. 1, a spin moment transfer (SMT) MRAM cell 100consists of an MTJ element 105 and a Metal Oxide Semiconductor (MOS)gating transistor 110. The MTJ element 105 is composed of a pinnedferromagnetic layer 102 and a free ferromagnetic layer 104, and a tunnelbarrier layer 103. The drain of the gating transistor 110 is connectedthrough a nonmagnetic layer to the pinned ferromagnetic layer 102. Thefree ferromagnetic layer 104 is connected to a bit line 115 and thesource of the gating transistor 110 is connected the source line 120.The bit line 115 and source select line 120 are connected to the bipolarwrite pulse/read bias generator 125. The bipolar write pulse/read biasgenerator 125 provides the necessary programming current to the MTJelement 105 through the bit line 115 and the source select line 120. Thedirection being determined by logic state being programmed to the MTJelement 105.

The gate of the gating transistor 110 is connected to a word line 130.The word line 130 transfers a word line select voltage to the gate ofthe gating transistor 110 to activate the gating transistor 110 forreading or writing the logic state of the MTJ element 105. A senseamplifier 135 has one input terminal connected to the bit line and asecond input terminal connected to a voltage reference circuit. When theword line 130 has the word line select voltage activated to turn on thegating transistor 110, the bipolar write pulse/read bias generator 125generates a bias current that passes through MTJ element 105. A voltageis developed across the MTJ element 105 that is sensed by the senseamplifier 135 and compared with the reference voltage generator todetermine the logic state written to the MTJ element 105. This logicstate is transferred to the output terminal of the sense amplifier 135as to the data output signal 145.

Arrays of spin moment transfer (SMT) MRAM cell 100 are arranged in rowsand columns. Each row of the spin-transfer based magneto tunnel junctionmemory devices may have their source line 120 commonly connected to asource line selection circuit or tied to a ground reference point. Inother arrangements of an array of SMT MRAM cells 100, as shown in U.S.Patent Application 200/60018057 (Huai), the SMT MRAM cells 100 areorganized into an array having two bit lines. The two bit lines arestructures such that the current flowing perpendicularly through the MTJ105 is controlled by the difference of the bias voltages of the two bitlines for each spin moment transfer (SMT) MRAM cell 100. Tworeading/writing column selection circuits are provided to control thevoltages on the bit lines.

SUMMARY

An object of this disclosure is to provide an array of SMT MRAM cellswith paired columns of the SMT MRAM cells having shared bit lines withmeans for lowering the resistance of the shared bit lines.

Another object of this disclosure is inhibiting program disturbance of anon-selected column of a pair of columns of the SMT MRAM cells.

To accomplish at least one of these objects, an array of SMT MRAM cellsis arranged in rows and columns. An array of SMT MRAM cells is arrangedin rows and columns. Each of the columns of SMT MRAM cells is associatedwith one of its adjacent columns of SMT MRAM cells. Each column isconnected to a true data bit line and each associated pair of columns ofSMT MRAM cells is connected to a shared complement data bit line. Ashunting switch device is connected between each of the true data bitlines and the shared complement data bit line for selectively connectingone of the true data bit lines to the shared complement data bit line toeffectively reduce the resistance of the complement data bit line and toeliminate program disturb effects in adjacent non-selected columns ofthe SMT MRAM cells. An activation terminal of each of the shuntingswitch device is connected to a column address decoder such that theshunting switch device is activated to connect the true data bit lineassociated with the non-selected column in parallel with the complementdata bit line. The shared complement data bit line may be wider than thetrue data bit line to further lower the resistance of the sharedcomplement data bit line. In some embodiments the shared complement databit line may be twice the dimension of the true data bit line.

In other embodiments, a bit line structure for connecting columns of SMTMRAM cells within an array of SMT MRAM cells has a true data bit lineconnected to an MTJ device of each SMT MRAM cell of each column of theSMT MRAM cells. A complement data bit line is connected to a source of agating transistor of each SMT MRAM cell of the each column of the SMTMRAM cells. The bit line structure has a shunting switch transistorconnected between the true data bit line and the complement data bitline of the associated pairs of columns of the SMT MRAM cells. Theshunting switch transistors have an activation terminal that, whenactivated, connects the true data bit line of an unselected column ofthe SMT MRAM cells in parallel with the shared complement data bit lineto effectively reduce program disturb effects in the unselected columnof SMT MRAM cells. The shared complement data bit line may be wider thanthe true data bit line to further lower the resistance of the sharedcomplement data bit line. The shared complement data bit line may betwice the dimension of the true data bit line.

In other embodiments, a method for reducing resistance of a shared bitline and reducing program disturb effects of unselected columns of SMTMRAM cells in an array of SMT MRAM cells begins by providing an array ofSMT MRAM cells where columns of the SMT MRAM cells are mutuallyconnected to a shared complement data bit line through the source of agating transistor of each of the SMT MRAM cells of the pair of columnsof SMT MRAM cells. The shared complement data bit line may be wider thanthe true data bit line to further lower the resistance of the sharedcomplement data bit line. In some embodiments the shared complement databit line may be twice the dimension of the true data bit line.

Each of the SMT MRAM cells of each column of the SMT MRAM cells isconnected to a true data bit line through an MTJ device within the SMTMRAM cells. A source of a gating transistor of the pair of adjacentcolumns of SMT MRAM cells is connected to a complement data bit line. Ashunting switch transistor is connected between the true data bit lineand the complement data bit line of the associated pairs of columns ofthe SMT MRAM cells. During a program operation, an address is decoded toselect a row and columns of the array of SMT MRAM cells. An activationterminal of each of the shunting switch transistor of each unselectedcolumn of the array of SMT MRAM cells is initiated to turn on theshunting switch transistors to connect the true data bit line of theunselected column of the SMT MRAM cells in parallel with the sharedcomplement data bit line to effectively reduce program disturb effectsin the unselected column of SMT MRAM cells. The programming drivecurrent is then activated to program the selected SMT MRAM cells of theselected rows and columns.

Further, in other embodiments, an array of SMT MRAM cells is arranged inrows and columns. Each of the columns of SMT MRAM cells is associatedwith one of its adjacent columns of SMT MRAM cells. Each column isconnected to a true data bit line and to a complement data bit line.

A shunting switch device is connected between the true data bit line andthe complement data bit line of the connected columns of SMT MRAM cellsfor selectively connecting one of the true data bit lines to thecomplement data bit line to effectively reduce the resistance of thecomplement data bit line and to eliminate program disturb effects inadjacent non-selected columns of the SMT MRAM cells. The complement databit lines are connected such that they are shared during a programoperation to further reduce the resistance of the complement data bitlines. An activation terminal of each of the shunting switch devices isconnected to a column address decoder such that the shunting switchdevice is activated to connect the true data bit line associated withthe non-selected column in parallel with the complement data bit line.

Still further, in other embodiments, an array of SMT MRAM cells isarranged in rows and columns. Each of the columns of SMT MRAM cells isassociated with one of its adjacent columns of SMT MRAM cells. Eachcolumn is connected to a true data bit line and to a complement data bitline. At least one true data bit line shunting switch device isconnected between the true data bit line and the complement data bitline of the connected columns of SMT MRAM cells for selectivelyconnecting one of the true data bit lines to the complement data bitline. The complement data bit lines of the associated adjacent columnshave at least one complement data bit line shunting switch deviceconnected between the adjacent complement data bit lines such that theyare shared during a program operation to further reduce the resistanceof the complement data bit lines. An activation terminal of each of theshunting switch devices is connected to a column address decoder suchthat the shunting switch device is activated to connect the twocomplement data bit lines and the true data bit line associated with thenon-selected column in parallel to effectively reduce the resistance ofthe complement data bit line and to eliminate program disturb effects inadjacent non-selected columns of the SMT MRAM cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional diagram of a SMT MRAM memory cell and itsperipheral circuitry of the related art.

FIG. 2 is a functional diagram of a SMT MRAM memory cell and itsperipheral circuitry.

FIG. 3 is a schematic diagram of an embodiment of an array of SMT MRAMmemory cells.

FIG. 4 is block diagram of an embodiment of an SMT MRAM memory device.

FIG. 5 is a flow diagram for a method to effectively reduce programdisturb effects in the unselected column of SMT MRAM cells.

FIG. 6 is a schematic diagram of another embodiment of an array of SMTMRAM memory cells having shunting switch transistors.

FIG. 7 is a schematic diagram of still another embodiment of an array ofSMT MRAM memory cells having shunting switch transistors.

DETAILED DESCRIPTION

The embodiments of SMT MRAM cell arrays have columns of SMT MRAM memorycells with pairs of bit lines, for the sake of convention, have one ofthe bit line referred to as a true data bit line and the other bit linereferred to as the complement data bit line. In the related art, asdescribed in Huai, FIG. 9, each column of cells has a pair of bit lines.Such architecture has too many bit lines and the bit line connecting tothe source sides of gating transistor 110 of FIG. 2 is highly resistive.High bit line resistance puts constraint on how many cells that may begrouped in a bthic array with decoders and drivers. In embodiments ofthis disclosure, adjacent pairs of columns are connected to share a bitthe complement data bit lines. The complement data bit lines areeffectively merged to form the complement data bit lines. Therefore, insome embodiments, the complement data bit lines are formed to be muchwider and therefore less resistive. This permits a larger and moreefficient array in terms of area. However, in the shared complement databit line structure, the adjacent SMT MRAM memory cell of an SMT MRAMmemory cell being programmed will be disturbed during programming. Toeffectively reduce program disturb effects in the unselected column ofSMT MRAM cells, shunting switch transistors are added between each ofthe true data bit lines and the shared complement data bit lines.

Referring to FIG. 2, the structure of the SMT MRAM memory cell isessentially identical to that of FIG. 1, except the source of the gatingtransistor 110 of the SMT MRAM memory cell 100 is connected to theshared complement data bit line 155. In the embodiments, the complementdata bit line 155 is structured to be in parallel with the true data bitline 150. The true data bit line 150 is connected to the freeferromagnetic layer 104 of the MTJ element 105. The true data bit line150 and the complement data bit line 155 are connected to THE bipolarwrite pulse/read bias generator 125. The complement data bit line 155 isshared with an identical SMT MRAM memory cell 100 in an adjacent columnof SMT MRAM memory cells 100.

The complement data bit line 155 that is connected to the source of thegating transistor 110, is the first metal layer line in the physicalconstruction of the SMT MRAM memory cell 100. The true data bit line 150is the last, or the top most metal line in the physical cell stack. Thefirst metal bit line of the complement data bit line 155 has to sharethe space with vias connecting the drain side of the gating transistor110 to the bottom plate 102 of MTJ element 105 thus forcing the firstmetal bit line of the complement data bit line 155 usually to bethinner. The first metal bit line of the complement data bit line 155being narrower and thinner are therefore much more resistive than thetop true data bit line 150. By sharing two adjacent complement data bitlines 155, the width of shared line is effectively wider by threetimes—two lines plus the spacing between the two adjacent complementdata bit lines 155. The disadvantage of doing so is that the SMT MRAMmemory cell 100 adjacent to the cell being programmed will see a disturbcondition because they share the same selected word line 130. Theshunting transistor (or transistors if we put more than one between thebit lines true and complement) will help to reduce this disturbcondition. The further reduction in resistance of the two adjacentcomplement data bit lines 155 comes from the neighboring true bit line150 is also in parallel with the complement bit line 155. But thisrequires more than one shunting transistor between the true andcomplement bit lines.

FIG. 3 illustrates an embodiment of an array 200 of the SMT MRAM memorycells 100. The SMT MRAM memory cells 100 are arranged into rows andcolumns to form the array 200. The MTJ element of each SMT MRAM memorycells 100 is connected to one of the true data bit lines 250 a, 259 b,250 n.

Adjacent columns of SMT MRAM memory cells 100 are associated with eachother. A shunting switch transistor 205 a, . . . , 205 n and 206 a, . .. , 206 n connects each true data bit line 250 a, 250 b, . . . , 250n−1, 250 n to its associated shared complement data bit line 255 a, . .. , 255 n. A first source/drain of each of the shunting switchtransistor 205 a, . . . , 205 n and 206 a, . . . , 206 n is connected tothe true data bit line 250 a, 250 b, . . . , 250 n−1, 250 n. The secondsource/drain of each of the shunting switch transistor 205 a, . . . ,205 n and 206 a, . . . , 206 n is connected to one shared complementdata bit line 255 a, . . . , 255 n. The gate of each of the shuntingswitch transistors 205 a, . . . , 205 n is connected to the in-phasecolumn address select bit Ay 210 and the gate of each of the shuntingswitch transistor 206 a, . . . , 206 n is connected to the out-of-phasecolumn address select bit Ay 212. The in-phase column address select bitAy and the out-of-phase column address select bit Ay 212 originate froma column or bit line decoder selector that decodes an address to selectthe columns of the array 200 for programming, reading, and erasing.

Each of the true data bit lines 250 a, 250 b, . . . , 250 n−1, 250 n isconnected to a first source/drain of a true data bit line switchtransistor 215 a, 215 b, . . . , 215 n−1, 215 n. The second source/drainof each of the true data bit line switch transistors 215 a, 215 b, . . ., 215 n−1, 215 n is connected to a true program data voltagedistribution line 247. Each shared complement data bit line 255 a, . . ., 255 n is connected to a first Source/drain of each of the complementdata bit line switch transistors 220 a, . . . , 220 n. The secondsource/drain of each of the complement data bit line switch transistors220 a, . . . , 220 n is connected to a complement data program voltagedistribution line 245. The gates of the true data bit line switchtransistors 215 a, 215 b, . . . , 215 n−1, 215 n are connected to thebit line decode select circuit 227. The decode select circuit 225receives an address, decodes the address and activates the appropriategate of the true data bit line switch transistors 215 a, 215 b, . . . ,215 n−1, 215 n to activate the selected column or columns forprogramming, erasing, and reading the selected SMT MRAM memory cells100.

Each of the complement data bit lines 255 a, 255 b, . . . , 255 n−1, 255n is connected to a first source/drain of a complement data bit lineswitch transistor 220 a, 220 b, . . . , 220 n−1, 220 n. The secondsource/drain of each of the complement data bit line switch transistors220 a, 220 b, . . . , 220 n−1, 220 n is connected to a program voltagedistribution line 245. Each shared complement data bit line 255 a, . . ., 255 n is connected to a first source/drain of each of the complementdata bit line switch transistors 220 a, . . . , 220 n. The secondsource/drain of each of the complement data bit line switch transistors220 a, . . . , 220 n is connected to a program voltage distribution line245. The gates of the complement data bit line switch transistors 220 a,220 b, . . . , 220 n−1, 220 n are connected to the bit line decodeselect circuit 225. As above, the decode select circuit 225 receives anaddress, decodes the address and activates the appropriate gate of thecomplement data bit line switch transistors 220 a, 220 b, . . . , 220n−1, 220 n to activate the selected column or columns for programming,erasing, and reading the selected SMT MRAM memory cells 100.

During programming of selected SMT MRAM memory cells 100, the shuntingswitch transistors 205 a, . . . , 205 n are activated to effectivelyplace unselected true data bit line 250 a, 250 b, . . . , 250 n−1, 250 nin parallel with the shared complement data bit line 255 a, . . . , 255n for each paired columns of the SMT MRAM memory cells 100. By placingthe true data bit line 250 a, 250 b, . . . , 250 n−1, 250 n in parallelwith the shared complement data bit line 255 a, . . . , 255 n, theresistance of the shared complement data bit line 255 a, . . . , 255 nis effectively decreased and prevents disturb program currents frompassing through the unselected SMT MRAM cells 100.

FIG. 4 is block diagram of an embodiment of an SMT MRAM memory deviceshowing a shared bit line structure with shunting switch transistorsbetween the true data bit lines and the shared complement data bitlines. The SMT MRAM memory device has an array of SMT MRAM memory cells100 that is formed of multiple sub-arrays 200 of SMT MRAM memory cells100. The SMT MRAM memory cells 100 are formed in rows and columns withthe structure as described in FIG. 2. With each row of the SMT MRAMmemory cells 100 are connected to one of the word lines 315 a, . . . ,315 m, 316 a, . . . , 316 m. Each column of the SMT MRAM memory cells100 is connected to one of the true data bit lines 320 a, 320 b, . . . ,320 n−1, 320 n, 321 a, 321 b, . . . , 321 n−1, 321 n, and 322 a, 322 b,322 n−1, 322 n. Adjacent columns are paired and connected to one of theshared complement data bit line 325 a, . . . , 325 m, 326 a, . . . , 326m, and 327 a, . . . , 327 m. The true data bit lines 320 a, 320 b, . . ., 320 n−1, 320 n, 321 a, 321 b, . . . , 321 n−1, 321 n, and 322 a, 322b, 322 n−1, 322 n are connected to their associated shared complementdata bit line 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . .. , 327 m through their respective shunting switch transistors 205 and206 to selectively connected the true data bit lines 320 a, 320 b, . . ., 320 n−1, 320 n, 321 a, 321 b, . . . , 321 n−1, 321 n, and 322 a, 322b, 322 n−1, 322 n of the unselected column of SMT MRAM memory cells 100to the associated shared complement data bit line 325 a, . . . , 325 m,326 a, . . . , 326 m, and 327 a, . . . , 327 m as described above.

The true data bit lines 320 a, 320 b, . . . , 320 n−1, 320 n, 321 a, 321b, 321 n−1, 321 n, and 322 a, 322 b, . . . , 322 n−1, 322 n areconnected to the bit line decode selector circuit 305 a. The sharedcomplement data bit line 325 a, . . . , 325 m, 326 a, . . . , 326 m, and327 a, . . . , 327 m are connected to the bit line decode selectorcircuit 305 b The bit line decode selector circuits 305 a and 305 b areconnected to the bit line decode circuit 355 The bit line decode circuitreceives the external address lines 365 and the external control lines360 and decodes the decoded address 370 and transmits the decodedaddress 370 to the bit line decode selector circuits 305 a and 305 b toselect the desired columns of selected sub-arrays 200 of the SMT MRAMmemory cells 100.

The write/read generator 335 receives the clock timing signal 345 andthe data input signal 350 and conditions and amplifies the data inputsignal 350 to form the true program data D_(w) 375 and the complementdata program 376. The true program data D_(w) 375 and the complementdata program D_(w) 376 are transferred respectively through the bit linedecode selector circuits 305 a and 305 b to the appropriate true databit lines 320 a, 320 b, . . . , 320 n−1, 320 n, 321 a, 321 b, . . . ,321 n−1, 321 n, and 322 a, 322 b, . . . , 322 n−1, 322 n and the sharedcomplement data bit lines 325 a, . . . , 325 m, 326 a, . . . , 326 m,and 327 a, . . . , 327 m.

During a programming operation, the shunting switch transistors 205 and206 of the unselected columns are activated to shunt the true data bitlines 320 a, 320 b, . . . , 320 n−1, 320 n, 321 a, 321 b, . . . , 321n−1, 321 n, and 322 a, 322 b, 322 n−1, 322 n of the unselected columnsto shared complement data bit lines 325 a, . . . , 325 m, 326 a, . . . ,326 m, and 327 a, . . . , 327 m to prevent disturb program currents frompassing through the unselected SMT MRAM cells 100 and to furtherdecrease the effective resistance of the complement data bit lines 325a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m.

During a read operation, a read current is passed from the bit linedecode selector 305 a through the selected true data bit lines 320 a,320 b, . . . , 320 n−1, 320 n, 321 a, 321 b, . . . , 321 n−1, 321 n, and322 a, 322 b, . . . , 322 n−1, 322 n to the MTJ of the SMT MRAM memorycells 100 to the shared complement data bit line 325 a, . . . , 325 m,326 a, . . . , 326 m, and 327 a, . . . , 327 m to the bit line decodeselector 305 b. The sense amplifiers are connected to the through thebit line decode selector 305 a to sense the voltage developed across theMTJ of the selected SMT MRAM memory cells 100 to detect the data storedin the selected SMT MRAM 100. The data driver 385 receives the captureddata conditions and amplifies the data to generate the output data 390that is transferred to external circuitry.

Refer now to FIG. 5 for a discussion of an embodiment of a method toreduce the resistance of a complement data bit line during a programmingoperation and to effectively reduce program disturb effects inunselected columns of SMT MRAM memory cells. A provided array of SMTMRAM memory cells is structured and operates as described in FIG. 3where columns of the SMT MRAM cells are mutually connected to a sharedcomplement data bit line through the source of a gating transistor ofeach of the SMT MRAM cells of the pair of columns of SMT MRAM cells.Each of the SMT MRAM cells of each column of the SMT MRAM cells isconnected to a true data bit line. Each of the true data bit lines isconnected to an MTJ device within the SMT MRAM cells. A source of agating transistor of the pair of adjacent columns of SMT MRAM cells isconnected to a complement data bit line. A shunting switch transistor isconnected between the true data bit line and the complement data bitline of the associated pairs of columns of the SMT MRAM cells. During aprogram operation, an address is decoded (Box 400) to select a row (Box405) and columns (Box 410) of the array of SMT MRAM cells. A gatingterminal of each of the shunting switch transistor of each unselectedcolumn of the array of SMT MRAM cells is activated (Box 415) to turn onthe shunting switch transistors to connect the true data bit line of theunselected columns of the SMT MRAM cells in parallel with the sharedcomplement data bit line to effectively reduce program disturb effectsin the unselected column of SMT MRAM cells. The programming drivecurrent is then activated (Box 420) to program the selected SMT MRAMcells of the selected rows and columns.

FIG. 6 illustrates an alternate embodiment of an array 200 of the SMTMRAM memory cells 100. The SMT MRAM memory cells 100 are arranged intorows and columns to form the array 200 as described above in FIG. 3. TheMTJ element of each SMT MRAM memory cells 100 is connected to one of thetrue data bit lines 250 a, 259 b, . . . , 250 n and to one of thecomplement data bit line 500 a, . . . , 500 n and, 501 a, . . . , 501 n.

Adjacent columns of SMT MRAM memory cells 100 are associated with eachother. A shunting switch transistor 505 a, . . . , 505 n and 506 a, . .. , 506 n connects each true data bit line 250 a, 250 b, . . . , 250n−1, 250 n to its associated complement data bit line 500 a, . . . , 500n and 501 a, . . . , 501 n. A first source/drain of each of the shuntingswitch transistors 505 a, . . . , 505 n and 506 a, . . . , 506 n isconnected to the true data bit line 250 a, 250 b, . . . , 250 n−1, 250n. The second source/drain of each of the shunting switch transistors505 a, . . . , 505 n and 506 a, . . . , 506 n is connected to oneassociated complement data bit line 500 a, . . . , 500 n and 501 a, . .. , 501 n. The gate of each of the shunting switch transistors 505 a, .. . , 505 n is connected to the in-phase column address select bit Ay210 and the gate of each of the shunting switch transistor 506 a, . . ., 506 n is connected to the out-of-phase column address select bit Ay212. The in-phase column address select bit Ay and the out-of-phasecolumn address select bit Ay 212 originate from a column or bit linedecoder selector that decodes an address to select the columns of thearray 200 for programming, reading, and erasing.

Each of the true data bit lines 250 a, 250 b, . . . , 250 n−1, 250 n isconnected to a first source/drain of a true data bit line switchtransistor 215 a, 215 b, . . . , 215 n−1, 215n. The second source/drainof each of the true data bit line switch transistors 215 a, 215 b, . . ., 215 n−1, 215 n is connected to a true program data voltagedistribution line 247. Each shared complement data bit line 500 a, . . ., 500 n and 501 a, . . . , 501 n is connected to a first source/drain ofeach of the complement data bit line switch transistors 220 a, . . . ,215 n. The second source/drain of each of the complement data bit lineswitch transistors 220 a, . . . , 215 n is connected to a complementdata program voltage distribution line 245. The gates of the true databit line switch transistors 215 a, 215 b, . . . , 215 n−1, 215 n areconnected to the bit line decode select circuit 225. The decode selectcircuit 225 receives an address, decodes the address and activates theappropriate gate of the true data bit line switch transistors 215 a, 215b, . . . , 215 n−1, 215 n to activate the selected column or columns forprogramming, erasing, and reading the slected SMT MRAM memory cells 100.

Each of the complement data bit lines 500 a, . . . , 500 n is connectedto a first source/drain of a complement data bit line switch transistor520 a, . . . , 520 n and each of the complement data bit lines 501 a, .. . , 501 n is connected to the first source/drain of a complement databit line switch transistors 521 a, . . . , 521 n. The secondsource/drain of each of the complement data bit line switch transistors520 a, . . . , 520 n and 521 a, . . . , 521 n is connected to a programvoltage distribution line 245. The gates of the complement data bit lineswitch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n areconnected to the bit line decode select circuit 225. As above, thedecode select circuit 225 receives an address, decodes the address andactivates the appropriate gate of the complement data bit line switchtransistors 520 a, . . . , 520 n and 521 a, . . . , 521 n to activatethe selected column or columns for programming, erasing, and reading theselected SMT MRAM memory cells 100.

During programming of selected SMT MRAM memory cells 100, the shuntingswitch transistors 505 a, . . . , 505 n and 506 a, . . . , 506 n areselectively activated to effectively place unselected true data bitlines 250 a, 250 b, . . . , 250 n−1, 250 n in parallel with theirassociated complement data bit line 500 a, . . . , 500 n and 501 a, . .. , 501 n for each of the columns of the SMT MRAM memory cells 100. Byplacing the true data bit line 250 a, 250 b, . . . , 250 n−1, 250 n inparallel with the complement data bit line 500 a, . . . , 500 n and 501a, . . . , 501 n, the resistance of the complement data bit line 500 a,. . . , 500 n and 501 a, . . . , 501 n is effectively decreased andprevents disturb program currents from passing through the unselectedSMT MRAM cells 100. Further during programming. the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n ofthe unselected columns are activated to effectively place the complementdata bit line 500 a, . . . , 500 n and 501 a, . . . , 501 n of theselected column in parallel with the complement data bit line 500 a, . .. , 500 n and 501 a, . . . , 501 n of the associated adjacent unselectedcolumn of the SMT MRAM memory cells 100. The placing the complement databit lines 500 a, . . . , 500 n and 501 a, . . . , 501 n of theassociated adjacent selected and unselected bit lines in paralleleffectively reduces the resistance of the complement data bit line 500a, . . . , 500 n and 501 a, . . . , 501 n of the selected columns of SMTMRAM memory cells 100 and any magnetic field resulting in a programdisturb of the unselected SMT MRAM memory cells 100 is mitigated.

The bit line decode selector circuit 225 must be structured to activatethe complement data bit line switch transistors 520 a, . . . , 520 n and521 a, . . . , 521 n appropriately for the unselected complement databit line 500 a, . . . , 500 n and 501 a, . . . , 501 n to connectedselected and unselected complement data bit line 500 a, . . . , 500 nand 501 a, 501 n in parallel. The bit line decode selector circuit 225must further deactivate the true data bit line switch transistors 215 a,215 b, . . . , 215 n−1, 215 n for the unselected true data bit lines 250a, 250 b, . . . , 250 n−1, 250 n to prevent the true program datavoltage distribution line 247 from being applied to the unselected truedata bit lines 450 a, 250 b, . . . , 250 n−1, 250 n and thus to theselected and unselected complement data bit lines 500 a, . . . , 500 nand 501 a, . . . , 501 n.

FIG. 7 illustrates a generalized embodiment of an array 200 of the SMTMRAM memory cells 100. The SMT MRAM memory cells 100 are arranged intorows and columns to form the array 200 as described above in FIGS. 3 and6. The MTJ element of each SMT MRAM memory cells 100 is connected to oneof the true data bit lines 250 a, 259 b, . . . , 250 n and to one of thecomplement data bit line 500 a, . . . , 500 n and 501 a, . . . , 501 n.

Adjacent columns of SMT MRAM memory cells 100 are associated with eachother. A shunting switch transistor 600 a, . . . , 600 n, 601 a, . . . ,601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n connects each truedata bit line 250 a, 250 b, . . . , 250 n−1, 250 n to its associatedcomplement data bit line 500 a, . . . , 500 n and 501 a, . . . , 501 n.A first source/drain of each of the shunting switch transistors 600 a, .. . , 600 n, 601 a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . ., 606 n is connected to one of the true data bit lines 250 a, 250 b, . .. , 250 n−1, 250 n. The second source/drain of each of the shuntingswitch transistors 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, .. . , 605 n and 606 a, . . . , 606 n is connected to one associatedcomplement data bit line 500 a, . . . , 500 n and 501 a, . . . , 501 n.The gate of each of the shunting switch transistors 600 a, . . . , 600n, and 605 a, . . . , 605 n is connected to the in-phase column addressselect bit Ay 620 a and 620 b and the gate of each of the shuntingswitch transistor 601 a, . . . , 601 n and 606 a, . . . , 606 n isconnected to the out-of-phase column address select bit Ay 621 a and 621b. The in-phase column address select bit Ay 620 a and 620 b and theout-of-phase column address select bit Ay 621 a and 621 b originate froma column or bit line decoder selector that decodes an address to selectthe columns of the array 200 for programming, reading, and erasing. Inthe generalized embodiment there may be an number of the shunting switchtransistors 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, 605 n and606 a, . . . , 606 n placed in parallel between the true data bit lines250 a, 250 b, . . . , 250 n−1, 250 n and their associated complementdata bit lines 500 a, . . . , 500 n and 501 a, . . . , 501 n with two ofthe shunting switch transistors 600 a, . . . , 600 n, 601 a, . . . , 601n, 605 a, . . . , 605 n and 606 a, . . . , 606 n connected between eachof the true data bit line 250 a, 250 b, . . . , 250 n−1, 250 n and theirassociated complement data bit line 500 a, . . . , 500 n and 501 a, . .. , 501 n.

Each of the complement data bit lines 500 a, . . . , 500 n and 501 a, .. . , 501 n of the associated columns of'SMT MRAM's 100 has a pair ofcomplement bit line shunting transistors 615 a, . . . , 615 n and 616 a,. . . , 616 n. Again as described above, in the generalized embodiment,the number of complement bit line shunting transistors 615 a, . . . ,615 n and 616 a, . . . , 616 n may be any number to assist in reducingthe resistance of the complement data bit line 500 a, . . . , 500 n and501 a, . . . , 501 n, with the two of this illustration being exemplary.A first source/drain of the complement bit line shunting transistors 615a, . . . , 615 n and 616 a, . . . , 616 n is connected to a first of thecomplement data bit lines 500 a, . . . , 500 n and 501 a, . . . , 501 nand a second source/drain of the complement data bit line 500 a, . . . ,500 n and 501 a, . . . , 501 n being connected to a second of theassociated complement data bit lines 500 a, . . . , 500 n and 501 a, . .. , 501 n. The gates of the complement bit line shunting, transistors615 a, . . . , 615 n and 616 a, . . . , 616 n are connected to a programcommand signal to activate the connection of the associated complementdata bit line 500 a, . . . , 500 n and 501 a, . . . , 501 n through thecomplement bit line shunting transistors 615 a, 615 n and 616 a, . . . ,616 n during a program operation and to disconnect the complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 nduring read and erase operations.

As shown in FIG. 6, each of the true data bit lines 250 a, 250 b, . . ., 250 n−1, 250 n is connected to a first source/drain of a true data bitline switch transistor 215 a, 215 b, . . . , 215 n−1, 215 n. The secondsource/drain of each of the true data bit line switch transistors 215 a,215 b, . . . , 215 n−1, 215 n is connected to a true program datavoltage distribution line 247. Each shared complement data it line 500a, . . . , 500 n and 501 a, . . . , 501 n is connected to a firstsource/drain of each of the complement data bit line switch transistors220 a, . . . , 215 n. The second source/drain of each of the complementdata bit line switch transistors 220 a, . . . , 215 n is connected to acomplement data program voltage distribution line 245. The gates of thetrue data bit line switch transistors 215 a, 215 b, . . . , 215 n−1, 215n are connected to the bit line decode select circuit 225. The decodeselect circuit 225 receives, an address, decodes the address andactivates the appropriate gate of the true data bit line switchtransistors 215 a, 215 b, . . . , 215 n−1, 215 n to activate theselected column or columns for programming, erasing, and reading theselected SMT MRAM memory cells 100.

Further, as shown in FIG. 6, each of the complement data bit lines 500a, . . . , 500 n is connected to a first source/drain of a complementdata bit line switch transistor 520 a, . . . , 520 n and each of thecomplement data bit lines 501 a, . . . , 501 n is connected to the firstsource/drain of a complement data bit line switch transistors 521 a, . .. , 521 n. The second source/drain of each of the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n isconnected to a program voltage distribution line 245. The gates of thecomplement data bit line switch transistors 220 a, 220 b, . . . , 220n−1, 220 n are connected to the bit line decode select circuit 225. Asabove, the decode select circuit 225 receives an address, decodes theaddress and activates the appropriate gate of the complement data bitline switch transistors 2 520 a, . . . , 520 n and 521 a, . . . , 521 nto activate the selected column or columns for programming, erasing, andreading the selected SMT MRAM memory cells 100.

During programming of selected SMT MRAM memory cells 100, the in-phasecolumn address select bit Ay 620 a and 620 b and the out-of-phase columnaddress select bit Ay 621 a and 621 b are selectively activated to turnon the selected shunting switch transistors 600 a, . . . , 600 n, 601 a,. . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n toeffectively place unselected true data bit lines 250 a, 250 b, . . . ,250 n−1, 250 n in parallel with their associated complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n for each of thecolumns of the SMT MRAM memory cells 100. The Program command signals625 a and 625 b are activated to turn on the selected complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 nplace the complement data bit lines 500 a, . . . , 500 n and 501 a, . .. , 501 n of the associated column pairs of the SMT MRAM memory cells100 in parallel to further reduce the resistance of the complement databit line 500 a, . . . , 500 n and 501 a, . . . , 501 n.

By placing the true data bit line 250 a, 250 b, . . . , 250 n−1, 250 nin parallel With the complement data bit line 500 a, . . . , 500 n and501 a, . . . , 501 n, the resistance of the complement data bit line 500a, . . . , 500 n and 501 a, . . . , 501 n is effectively decreased andany magnetic field resulting in a program disturb of the unselected SMTMRAM memory cells 100 is mitigated.

The bit line decode selector circuit 225 must deactivate the true databit line switch transistors 215 a, 215 b, . . . , 215 n−1, 215 n for theunselected true data bit lines 250 a, 250 b, . . . , 250 n−1, 250 n toprevent the true program data voltage distribution line 247 from beingapplied to the unselected true data bit lines 250 a, 250 b, . . . , 250n−1, 250 n and thus to the selected and unselected complement data bitlines 500 a, . . . , 500 n and 501 a, . . . , 501 n.

The placing of the shunting switch transistors 600 a, . . . , 600 n, 601a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n and thecomplement bit line shunting transistors 615 a, . . . , 615 n and 616 a,. . . , 616 n in the various locations through out the array 200 of SMTMRAM memory cells 100 of FIGS. 3, 4, 6, and 7 as stated above decreasesthe resistance of the complement data bit lines 500 a, . . . , 500 n and501 a, . . . , 501 n, therefore a larger and more efficient array interms of area is now formed.

While this disclosure has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the disclosure.

What is claimed is:
 1. An SMT MRAM device comprising: SMT MRAM memorycells arranged in an array of rows and columns such that each of thecolumns of SMT MRAM cells is associated with one of its adjacent columnsof SMT MRAM cells. a plurality of true data bit lines where each of thetrue data bit lines is connected to one adjacent column; a plurality ofcomplement data bit lines, wherein each of the plurality of complementdata bit lines are connected with each SMT MRAM cell of a pair ofcolumns of the SMT MRAM cells such that each of the plurality ofcomplement data bit lines is shared with the pair of columns of the SMTMRAM cells; and a plurality of shunting switch devices, wherein each ofthe shunting switch devices is connected between one of the true databit lines and the shared complement data bit line for selectivelyconnecting one of the true data bit lines to the shared complement databit line to effectively reduce the resistance of the complement data bitline and to eliminate program disturb effects in adjacent non-selectedcolumns of the SMT MRAM cells.
 2. The SMT MRAM device of claim 1 furthercomprising a column address decoder in communication with an activationterminal of each of the shunting switch devices such that the shuntingswitch device is activated to connect the true data bit line associatedwith the non-selected column in parallel with the complement data bitline.
 3. The SMT MRAM device of claim 1 wherein the shared complementdata bit line is wider than the true data bit line to further lower theresistance of the shared complement data bit line.
 4. The SMT MRAMdevice of claim 3 wherein the shared complement data bit line is twicethe dimension of the true data bit line.
 5. The array of SMT MRAM cellsof claim 3 further comprising means for selectively connecting the twoadjacent complement bit lines in parallel to merge the two adjacentcomplement bit lines to appear much wider and therefore less resistiveto permit a larger and more area efficient array of SMT MRAM cells.